// Peripheral: EXTI_Periph  External Interrupt/Event Controller.
// Instances:
//  EXTI  mmap.EXTI_BASE
// Registers:
//  0x00 32  IMR1   Interrupt mask register.
//  0x04 32  EMR1   Event mask register.
//  0x08 32  RTSR1  Rising trigger selection register.
//  0x0C 32  FTSR1  Falling trigger selection register.
//  0x10 32  SWIER1 Software interrupt event register.
//  0x14 32  PR1    Pending register.
//  0x20 32  IMR2   Interrupt mask register.
//  0x24 32  EMR2   Event mask register.
//  0x28 32  RTSR2  Rising trigger selection register.
//  0x2C 32  FTSR2  Falling trigger selection register.
//  0x30 32  SWIER2 Software interrupt event register.
//  0x34 32  PR2    Pending register.
// Import:
//  stm32/o/f303xe/mmap
package exti

// DO NOT EDIT THIS FILE. GENERATED BY stm32xgen.

const (
	IL0     IMR1 = 0x01 << 0       //+ Interrupt Mask on line 0.
	IL1     IMR1 = 0x01 << 1       //+ Interrupt Mask on line 1.
	IL2     IMR1 = 0x01 << 2       //+ Interrupt Mask on line 2.
	IL3     IMR1 = 0x01 << 3       //+ Interrupt Mask on line 3.
	IL4     IMR1 = 0x01 << 4       //+ Interrupt Mask on line 4.
	IL5     IMR1 = 0x01 << 5       //+ Interrupt Mask on line 5.
	IL6     IMR1 = 0x01 << 6       //+ Interrupt Mask on line 6.
	IL7     IMR1 = 0x01 << 7       //+ Interrupt Mask on line 7.
	IL8     IMR1 = 0x01 << 8       //+ Interrupt Mask on line 8.
	IL9     IMR1 = 0x01 << 9       //+ Interrupt Mask on line 9.
	IL10    IMR1 = 0x01 << 10      //+ Interrupt Mask on line 10.
	IL11    IMR1 = 0x01 << 11      //+ Interrupt Mask on line 11.
	IL12    IMR1 = 0x01 << 12      //+ Interrupt Mask on line 12.
	IL13    IMR1 = 0x01 << 13      //+ Interrupt Mask on line 13.
	IL14    IMR1 = 0x01 << 14      //+ Interrupt Mask on line 14.
	IL15    IMR1 = 0x01 << 15      //+ Interrupt Mask on line 15.
	IL16    IMR1 = 0x01 << 16      //+ Interrupt Mask on line 16.
	IL17    IMR1 = 0x01 << 17      //+ Interrupt Mask on line 17.
	IL18    IMR1 = 0x01 << 18      //+ Interrupt Mask on line 18.
	IL19    IMR1 = 0x01 << 19      //+ Interrupt Mask on line 19.
	IL20    IMR1 = 0x01 << 20      //+ Interrupt Mask on line 20.
	IL21    IMR1 = 0x01 << 21      //+ Interrupt Mask on line 21.
	IL22    IMR1 = 0x01 << 22      //+ Interrupt Mask on line 22.
	IL23    IMR1 = 0x01 << 23      //+ Interrupt Mask on line 23.
	IL24    IMR1 = 0x01 << 24      //+ Interrupt Mask on line 24.
	IL25    IMR1 = 0x01 << 25      //+ Interrupt Mask on line 25.
	IL26    IMR1 = 0x01 << 26      //+ Interrupt Mask on line 26.
	IL27    IMR1 = 0x01 << 27      //+ Interrupt Mask on line 27.
	IL28    IMR1 = 0x01 << 28      //+ Interrupt Mask on line 28.
	IL29    IMR1 = 0x01 << 29      //+ Interrupt Mask on line 29.
	IL30    IMR1 = 0x01 << 30      //+ Interrupt Mask on line 30.
	IL31    IMR1 = 0x01 << 31      //+ Interrupt Mask on line 31.
	IMR1ALL IMR1 = 0xFFFFFFFF << 0 //  Interrupt Mask All.
)

const (
	IL0n  = 0
	IL1n  = 1
	IL2n  = 2
	IL3n  = 3
	IL4n  = 4
	IL5n  = 5
	IL6n  = 6
	IL7n  = 7
	IL8n  = 8
	IL9n  = 9
	IL10n = 10
	IL11n = 11
	IL12n = 12
	IL13n = 13
	IL14n = 14
	IL15n = 15
	IL16n = 16
	IL17n = 17
	IL18n = 18
	IL19n = 19
	IL20n = 20
	IL21n = 21
	IL22n = 22
	IL23n = 23
	IL24n = 24
	IL25n = 25
	IL26n = 26
	IL27n = 27
	IL28n = 28
	IL29n = 29
	IL30n = 30
	IL31n = 31
)

const (
	EL0  EMR1 = 0x01 << 0  //+ Event Mask on line 0.
	EL1  EMR1 = 0x01 << 1  //+ Event Mask on line 1.
	EL2  EMR1 = 0x01 << 2  //+ Event Mask on line 2.
	EL3  EMR1 = 0x01 << 3  //+ Event Mask on line 3.
	EL4  EMR1 = 0x01 << 4  //+ Event Mask on line 4.
	EL5  EMR1 = 0x01 << 5  //+ Event Mask on line 5.
	EL6  EMR1 = 0x01 << 6  //+ Event Mask on line 6.
	EL7  EMR1 = 0x01 << 7  //+ Event Mask on line 7.
	EL8  EMR1 = 0x01 << 8  //+ Event Mask on line 8.
	EL9  EMR1 = 0x01 << 9  //+ Event Mask on line 9.
	EL10 EMR1 = 0x01 << 10 //+ Event Mask on line 10.
	EL11 EMR1 = 0x01 << 11 //+ Event Mask on line 11.
	EL12 EMR1 = 0x01 << 12 //+ Event Mask on line 12.
	EL13 EMR1 = 0x01 << 13 //+ Event Mask on line 13.
	EL14 EMR1 = 0x01 << 14 //+ Event Mask on line 14.
	EL15 EMR1 = 0x01 << 15 //+ Event Mask on line 15.
	EL16 EMR1 = 0x01 << 16 //+ Event Mask on line 16.
	EL17 EMR1 = 0x01 << 17 //+ Event Mask on line 17.
	EL18 EMR1 = 0x01 << 18 //+ Event Mask on line 18.
	EL19 EMR1 = 0x01 << 19 //+ Event Mask on line 19.
	EL20 EMR1 = 0x01 << 20 //+ Event Mask on line 20.
	EL21 EMR1 = 0x01 << 21 //+ Event Mask on line 21.
	EL22 EMR1 = 0x01 << 22 //+ Event Mask on line 22.
	EL23 EMR1 = 0x01 << 23 //+ Event Mask on line 23.
	EL24 EMR1 = 0x01 << 24 //+ Event Mask on line 24.
	EL25 EMR1 = 0x01 << 25 //+ Event Mask on line 25.
	EL26 EMR1 = 0x01 << 26 //+ Event Mask on line 26.
	EL27 EMR1 = 0x01 << 27 //+ Event Mask on line 27.
	EL28 EMR1 = 0x01 << 28 //+ Event Mask on line 28.
	EL29 EMR1 = 0x01 << 29 //+ Event Mask on line 29.
	EL30 EMR1 = 0x01 << 30 //+ Event Mask on line 30.
	EL31 EMR1 = 0x01 << 31 //+ Event Mask on line 31.
)

const (
	EL0n  = 0
	EL1n  = 1
	EL2n  = 2
	EL3n  = 3
	EL4n  = 4
	EL5n  = 5
	EL6n  = 6
	EL7n  = 7
	EL8n  = 8
	EL9n  = 9
	EL10n = 10
	EL11n = 11
	EL12n = 12
	EL13n = 13
	EL14n = 14
	EL15n = 15
	EL16n = 16
	EL17n = 17
	EL18n = 18
	EL19n = 19
	EL20n = 20
	EL21n = 21
	EL22n = 22
	EL23n = 23
	EL24n = 24
	EL25n = 25
	EL26n = 26
	EL27n = 27
	EL28n = 28
	EL29n = 29
	EL30n = 30
	EL31n = 31
)

const (
	TR0  RTSR1 = 0x01 << 0  //+ Rising trigger event configuration bit of line 0.
	TR1  RTSR1 = 0x01 << 1  //+ Rising trigger event configuration bit of line 1.
	TR2  RTSR1 = 0x01 << 2  //+ Rising trigger event configuration bit of line 2.
	TR3  RTSR1 = 0x01 << 3  //+ Rising trigger event configuration bit of line 3.
	TR4  RTSR1 = 0x01 << 4  //+ Rising trigger event configuration bit of line 4.
	TR5  RTSR1 = 0x01 << 5  //+ Rising trigger event configuration bit of line 5.
	TR6  RTSR1 = 0x01 << 6  //+ Rising trigger event configuration bit of line 6.
	TR7  RTSR1 = 0x01 << 7  //+ Rising trigger event configuration bit of line 7.
	TR8  RTSR1 = 0x01 << 8  //+ Rising trigger event configuration bit of line 8.
	TR9  RTSR1 = 0x01 << 9  //+ Rising trigger event configuration bit of line 9.
	TR10 RTSR1 = 0x01 << 10 //+ Rising trigger event configuration bit of line 10.
	TR11 RTSR1 = 0x01 << 11 //+ Rising trigger event configuration bit of line 11.
	TR12 RTSR1 = 0x01 << 12 //+ Rising trigger event configuration bit of line 12.
	TR13 RTSR1 = 0x01 << 13 //+ Rising trigger event configuration bit of line 13.
	TR14 RTSR1 = 0x01 << 14 //+ Rising trigger event configuration bit of line 14.
	TR15 RTSR1 = 0x01 << 15 //+ Rising trigger event configuration bit of line 15.
	TR16 RTSR1 = 0x01 << 16 //+ Rising trigger event configuration bit of line 16.
	TR17 RTSR1 = 0x01 << 17 //+ Rising trigger event configuration bit of line 17.
	TR18 RTSR1 = 0x01 << 18 //+ Rising trigger event configuration bit of line 18.
	TR19 RTSR1 = 0x01 << 19 //+ Rising trigger event configuration bit of line 19.
	TR20 RTSR1 = 0x01 << 20 //+ Rising trigger event configuration bit of line 20.
	TR21 RTSR1 = 0x01 << 21 //+ Rising trigger event configuration bit of line 21.
	TR22 RTSR1 = 0x01 << 22 //+ Rising trigger event configuration bit of line 22.
	TR29 RTSR1 = 0x01 << 29 //+ Rising trigger event configuration bit of line 29.
	TR30 RTSR1 = 0x01 << 30 //+ Rising trigger event configuration bit of line 30.
	TR31 RTSR1 = 0x01 << 31 //+ Rising trigger event configuration bit of line 31.
)

const (
	TR0n  = 0
	TR1n  = 1
	TR2n  = 2
	TR3n  = 3
	TR4n  = 4
	TR5n  = 5
	TR6n  = 6
	TR7n  = 7
	TR8n  = 8
	TR9n  = 9
	TR10n = 10
	TR11n = 11
	TR12n = 12
	TR13n = 13
	TR14n = 14
	TR15n = 15
	TR16n = 16
	TR17n = 17
	TR18n = 18
	TR19n = 19
	TR20n = 20
	TR21n = 21
	TR22n = 22
	TR29n = 29
	TR30n = 30
	TR31n = 31
)

const (
	TF0  FTSR1 = 0x01 << 0  //+ Falling trigger event configuration bit of line 0.
	TF1  FTSR1 = 0x01 << 1  //+ Falling trigger event configuration bit of line 1.
	TF2  FTSR1 = 0x01 << 2  //+ Falling trigger event configuration bit of line 2.
	TF3  FTSR1 = 0x01 << 3  //+ Falling trigger event configuration bit of line 3.
	TF4  FTSR1 = 0x01 << 4  //+ Falling trigger event configuration bit of line 4.
	TF5  FTSR1 = 0x01 << 5  //+ Falling trigger event configuration bit of line 5.
	TF6  FTSR1 = 0x01 << 6  //+ Falling trigger event configuration bit of line 6.
	TF7  FTSR1 = 0x01 << 7  //+ Falling trigger event configuration bit of line 7.
	TF8  FTSR1 = 0x01 << 8  //+ Falling trigger event configuration bit of line 8.
	TF9  FTSR1 = 0x01 << 9  //+ Falling trigger event configuration bit of line 9.
	TF10 FTSR1 = 0x01 << 10 //+ Falling trigger event configuration bit of line 10.
	TF11 FTSR1 = 0x01 << 11 //+ Falling trigger event configuration bit of line 11.
	TF12 FTSR1 = 0x01 << 12 //+ Falling trigger event configuration bit of line 12.
	TF13 FTSR1 = 0x01 << 13 //+ Falling trigger event configuration bit of line 13.
	TF14 FTSR1 = 0x01 << 14 //+ Falling trigger event configuration bit of line 14.
	TF15 FTSR1 = 0x01 << 15 //+ Falling trigger event configuration bit of line 15.
	TF16 FTSR1 = 0x01 << 16 //+ Falling trigger event configuration bit of line 16.
	TF17 FTSR1 = 0x01 << 17 //+ Falling trigger event configuration bit of line 17.
	TF18 FTSR1 = 0x01 << 18 //+ Falling trigger event configuration bit of line 18.
	TF19 FTSR1 = 0x01 << 19 //+ Falling trigger event configuration bit of line 19.
	TF20 FTSR1 = 0x01 << 20 //+ Falling trigger event configuration bit of line 20.
	TF21 FTSR1 = 0x01 << 21 //+ Falling trigger event configuration bit of line 21.
	TF22 FTSR1 = 0x01 << 22 //+ Falling trigger event configuration bit of line 22.
	TF29 FTSR1 = 0x01 << 29 //+ Falling trigger event configuration bit of line 29.
	TF30 FTSR1 = 0x01 << 30 //+ Falling trigger event configuration bit of line 30.
	TF31 FTSR1 = 0x01 << 31 //+ Falling trigger event configuration bit of line 31.
)

const (
	TF0n  = 0
	TF1n  = 1
	TF2n  = 2
	TF3n  = 3
	TF4n  = 4
	TF5n  = 5
	TF6n  = 6
	TF7n  = 7
	TF8n  = 8
	TF9n  = 9
	TF10n = 10
	TF11n = 11
	TF12n = 12
	TF13n = 13
	TF14n = 14
	TF15n = 15
	TF16n = 16
	TF17n = 17
	TF18n = 18
	TF19n = 19
	TF20n = 20
	TF21n = 21
	TF22n = 22
	TF29n = 29
	TF30n = 30
	TF31n = 31
)

const (
	SWI0  SWIER1 = 0x01 << 0  //+ Software Interrupt on line 0.
	SWI1  SWIER1 = 0x01 << 1  //+ Software Interrupt on line 1.
	SWI2  SWIER1 = 0x01 << 2  //+ Software Interrupt on line 2.
	SWI3  SWIER1 = 0x01 << 3  //+ Software Interrupt on line 3.
	SWI4  SWIER1 = 0x01 << 4  //+ Software Interrupt on line 4.
	SWI5  SWIER1 = 0x01 << 5  //+ Software Interrupt on line 5.
	SWI6  SWIER1 = 0x01 << 6  //+ Software Interrupt on line 6.
	SWI7  SWIER1 = 0x01 << 7  //+ Software Interrupt on line 7.
	SWI8  SWIER1 = 0x01 << 8  //+ Software Interrupt on line 8.
	SWI9  SWIER1 = 0x01 << 9  //+ Software Interrupt on line 9.
	SWI10 SWIER1 = 0x01 << 10 //+ Software Interrupt on line 10.
	SWI11 SWIER1 = 0x01 << 11 //+ Software Interrupt on line 11.
	SWI12 SWIER1 = 0x01 << 12 //+ Software Interrupt on line 12.
	SWI13 SWIER1 = 0x01 << 13 //+ Software Interrupt on line 13.
	SWI14 SWIER1 = 0x01 << 14 //+ Software Interrupt on line 14.
	SWI15 SWIER1 = 0x01 << 15 //+ Software Interrupt on line 15.
	SWI16 SWIER1 = 0x01 << 16 //+ Software Interrupt on line 16.
	SWI17 SWIER1 = 0x01 << 17 //+ Software Interrupt on line 17.
	SWI18 SWIER1 = 0x01 << 18 //+ Software Interrupt on line 18.
	SWI19 SWIER1 = 0x01 << 19 //+ Software Interrupt on line 19.
	SWI20 SWIER1 = 0x01 << 20 //+ Software Interrupt on line 20.
	SWI21 SWIER1 = 0x01 << 21 //+ Software Interrupt on line 21.
	SWI22 SWIER1 = 0x01 << 22 //+ Software Interrupt on line 22.
	SWI29 SWIER1 = 0x01 << 29 //+ Software Interrupt on line 29.
	SWI30 SWIER1 = 0x01 << 30 //+ Software Interrupt on line 30.
	SWI31 SWIER1 = 0x01 << 31 //+ Software Interrupt on line 31.
)

const (
	SWI0n  = 0
	SWI1n  = 1
	SWI2n  = 2
	SWI3n  = 3
	SWI4n  = 4
	SWI5n  = 5
	SWI6n  = 6
	SWI7n  = 7
	SWI8n  = 8
	SWI9n  = 9
	SWI10n = 10
	SWI11n = 11
	SWI12n = 12
	SWI13n = 13
	SWI14n = 14
	SWI15n = 15
	SWI16n = 16
	SWI17n = 17
	SWI18n = 18
	SWI19n = 19
	SWI20n = 20
	SWI21n = 21
	SWI22n = 22
	SWI29n = 29
	SWI30n = 30
	SWI31n = 31
)

const (
	PIF0  PR1 = 0x01 << 0  //+ Pending bit for line 0.
	PIF1  PR1 = 0x01 << 1  //+ Pending bit for line 1.
	PIF2  PR1 = 0x01 << 2  //+ Pending bit for line 2.
	PIF3  PR1 = 0x01 << 3  //+ Pending bit for line 3.
	PIF4  PR1 = 0x01 << 4  //+ Pending bit for line 4.
	PIF5  PR1 = 0x01 << 5  //+ Pending bit for line 5.
	PIF6  PR1 = 0x01 << 6  //+ Pending bit for line 6.
	PIF7  PR1 = 0x01 << 7  //+ Pending bit for line 7.
	PIF8  PR1 = 0x01 << 8  //+ Pending bit for line 8.
	PIF9  PR1 = 0x01 << 9  //+ Pending bit for line 9.
	PIF10 PR1 = 0x01 << 10 //+ Pending bit for line 10.
	PIF11 PR1 = 0x01 << 11 //+ Pending bit for line 11.
	PIF12 PR1 = 0x01 << 12 //+ Pending bit for line 12.
	PIF13 PR1 = 0x01 << 13 //+ Pending bit for line 13.
	PIF14 PR1 = 0x01 << 14 //+ Pending bit for line 14.
	PIF15 PR1 = 0x01 << 15 //+ Pending bit for line 15.
	PIF16 PR1 = 0x01 << 16 //+ Pending bit for line 16.
	PIF17 PR1 = 0x01 << 17 //+ Pending bit for line 17.
	PIF18 PR1 = 0x01 << 18 //+ Pending bit for line 18.
	PIF19 PR1 = 0x01 << 19 //+ Pending bit for line 19.
	PIF20 PR1 = 0x01 << 20 //+ Pending bit for line 20.
	PIF21 PR1 = 0x01 << 21 //+ Pending bit for line 21.
	PIF22 PR1 = 0x01 << 22 //+ Pending bit for line 22.
	PIF29 PR1 = 0x01 << 29 //+ Pending bit for line 29.
	PIF30 PR1 = 0x01 << 30 //+ Pending bit for line 30.
	PIF31 PR1 = 0x01 << 31 //+ Pending bit for line 31.
)

const (
	PIF0n  = 0
	PIF1n  = 1
	PIF2n  = 2
	PIF3n  = 3
	PIF4n  = 4
	PIF5n  = 5
	PIF6n  = 6
	PIF7n  = 7
	PIF8n  = 8
	PIF9n  = 9
	PIF10n = 10
	PIF11n = 11
	PIF12n = 12
	PIF13n = 13
	PIF14n = 14
	PIF15n = 15
	PIF16n = 16
	PIF17n = 17
	PIF18n = 18
	PIF19n = 19
	PIF20n = 20
	PIF21n = 21
	PIF22n = 22
	PIF29n = 29
	PIF30n = 30
	PIF31n = 31
)

const (
	IL32    IMR2 = 0x01 << 0 //+ Interrupt Mask on line 32.
	IL33    IMR2 = 0x01 << 1 //+ Interrupt Mask on line 33.
	IL34    IMR2 = 0x01 << 2 //+ Interrupt Mask on line 34.
	IL35    IMR2 = 0x01 << 3 //+ Interrupt Mask on line 35.
	IMR2ALL IMR2 = 0x0F << 0
)

const (
	IL32n = 0
	IL33n = 1
	IL34n = 2
	IL35n = 3
)

const (
	EL32 EMR2 = 0x01 << 0 //+ Event Mask on line 32.
	EL33 EMR2 = 0x01 << 1 //+ Event Mask on line 33.
	EL34 EMR2 = 0x01 << 2 //+ Event Mask on line 34.
	EL35 EMR2 = 0x01 << 3 //+ Event Mask on line 34.
	EM   EMR2 = 0x0F << 0
)

const (
	EL32n = 0
	EL33n = 1
	EL34n = 2
	EL35n = 3
)

const (
	TR32 RTSR2 = 0x01 << 0 //+ Rising trigger event configuration bit of line 32.
	TR33 RTSR2 = 0x01 << 1 //+ Rising trigger event configuration bit of line 33.
)

const (
	TR32n = 0
	TR33n = 1
)

const (
	TF32 FTSR2 = 0x01 << 0 //+ Falling trigger event configuration bit of line 32.
	TF33 FTSR2 = 0x01 << 1 //+ Falling trigger event configuration bit of line 33.
)

const (
	TF32n = 0
	TF33n = 1
)

const (
	SWI32 SWIER2 = 0x01 << 0 //+ Software Interrupt on line 32.
	SWI33 SWIER2 = 0x01 << 1 //+ Software Interrupt on line 33.
)

const (
	SWI32n = 0
	SWI33n = 1
)

const (
	PIF32 PR2 = 0x01 << 0 //+ Pending bit for line 32.
	PIF33 PR2 = 0x01 << 1 //+ Pending bit for line 33.
)

const (
	PIF32n = 0
	PIF33n = 1
)
